The present invention relates to Ferroelectric Random-Access Memories (FeRAMs), and to integrated circuits which include them.
Semiconductor memories normally use memory cells which are made as small as possible. As a result, the electrical signals which come out of these cells when the read operation is performed are extremely small. Thus, the sensing of semiconductor memories is a critical technology, which affects many other performance parameters. See B. Prince, Semiconductor Memories (2.ed 1991), which is hereby incorporated by reference. This is particularly true for ferroelectric memories.
One simple example of this is in the art of DRAM sensing. In a DRAM cell, information is stored by charging the cell capacitor to one of two voltages. By connecting the capacitor later to a bit line voltage which is intermediate between those two voltages, the stored charge, when dumped into one line of a bit line, will make the voltage on that bit line slightly different from that of a matched bit line. The sense amplifier amplifies this voltage difference to produce a large signal, which can be sensed by further amplifier stages (optional), and eventually by logic output stages.
In memory architectures generally, it is not only undesirable to have too little read margin (which can result in errors), but it is also undesirable to have too much read margin. (In this case it would be possible to shrink the cell further while still obtaining accuracy.) Thus, properly designing the reference input for the sense amplifier is critically important to memory optimization. Where the profile of the possible output signals of the cell is relatively complex, as with ferroelectric memories, optimal tracking of the sense amplifier""s reference is needed to provide the best possible margin of the sense amplifier. This translates directly into improvements in reliability and/or density.
Ferroelectric memories exploit the properties of ferroelectric materials, in which the induced electric field in the material is a nonlinear function of the applied voltage. See generally M. Lines and A. Glass, Principles and Applications of Ferroelectrics and Related Materials (1977), which is hereby incorporated by reference.
Ferroelectrics are analogous to ferromagnetic materials: just as the ferromagnetic material in a bar magnet can be permanently magnetized by applying a sufficiently strong magnetic field to it, and will thereafter act independently as a magnet, so a ferroelectric can acquire a fixed voltage gradient when a sufficiently strong electric field is applied to it.
This is useful in semiconductor memories, since ferroelectric materials have the potential to provide a non-volatile memory function. That is, after a ferroelectric material has been polarized in one direction, it will hold that polarization for a long time, and this provides non-volatile storage of information. (That is, the memory will retain its information even if it is not receiving any power supply voltage.) Ferroelectric random-access memories (xe2x80x9cFeRAMxe2x80x9ds) have therefore been a very active area of memory development. See generally, e.g., papers 25.1-25.7, 34.5, and 34.6 from the 1997 IEDM; all of which, and the references cited in them, are hereby incorporated by reference.
However, the sensing requirements of ferroelectric memories are difficult. Since the information in a ferroelectric memory cell is stored by polarization of the ferroelectric material (and not simply as charge), its read mechanism is actually quite different from that from a DRAM, SRAM, or floating-gate memory.
FIG. 5 shows the xe2x80x9cP/Vxe2x80x9d relation between stored charge density and applied voltage for a typical ferroelectric capacitor. Note that this curve has two values of charge for every value of voltage. Such curves are referred to as xe2x80x9chysteresisxe2x80x9d curves. Depending on which polarization state the ferroelectric capacitor is in, a cell with stored data will either be at the xe2x80x9c+Prxe2x80x9d point or at the xe2x80x9cxe2x88x92Prxe2x80x9d point. (xe2x80x9cPrxe2x80x9d is the spontaneous polarization density, and is measured in charge per unit area.) Note that the P/V hysteresis loop is nearly flat at these points, so a small change in voltage will not cause much charge transfer through the capacitor.)
FIG. 3 shows a conventional two-transistor, two-capacitor type of FeRAM cell. In this case the unit cell 100xe2x80x2, as indicated by a dotted line, includes two ferroelectric capacitors, each with its own pass transistor. The drive line DLn is connected to drive one terminal of the ferroelectric capacitor of each capacitor pair, and the wordline WLn is connected to open the pass transistors for both capacitors of a selected cell simultaneously. The two capacitor outputs then appear as a differential signal on the bit lines BL and BL , and are amplified in a conventional differential sense amplifier 102. In such a cell, the capacitors of the cell pair are always written into opposite states, so that a relatively strong differential signal can always be obtained. However, this memory architecture is obviously not very area-efficient.
FIG. 4 shows a further prior art cell. In this case, only one capacitor is used for memory in each cell. As indicated by the dotted line, a unit cell 100xe2x80x3 includes one transistor and one capacitor, and hence this is referred to as a xe2x80x9c1T1Cxe2x80x9d cell. Again, the wordline WLn is brought up to the positive logic level to turn on the pass transistor of the access cell. In this case the resulting output signal appears only as a single-ended signal on bitline BLm (or BLm ). The reference signal on the complementary bitline BL m (or BLm) is supplied by a dummy cell Dmb (or Dma). The dummy cell Dmb, in this example, has a capacitor Cd whose lower terminal (as shown by the dashed connection) receives a signal equal to that on the drive line DLn of the selected cells, and whose pass transistor is activated by the dummy word line WLdb. This provides a reference voltage on the complementary bit line BL m. However, this scheme is still quite difficult. The charge transfer through the ferroelectric capacitor of the selected cell, is dependent on its state of polarization and potentially different from that of a normal (paraelectric) capacitor like Cd.
Thus a disadvantage of the use of dummy cells in the prior art is that the dummy cell capacitor is not a ferroelectric capacitor, and thus its characteristics will not track those of a storage cell precisely. Moreover, the deposition and etch characteristics of the ferroelectric capacitor will not match those of a normal capacitor (which will typically have an oxide or oxynitride dielectric), so that process variation will not be identical between the two types of capacitor.
It is not practical to use a ferroelectric capacitor for the dummy cell, because complicated circuitry would be needed to drive the dummy cell properly. Moreover, the dummy cell consumes area.
Innovative Structures and Methods
The present application discloses a 1T1C ferroelectric memory architecture in which the read cycle includes two opposed pulses on the drive line: the first pulse provides a data-dependent signal out of the selected cell, and the second pulse restores the bit line to a level such that the DC bias voltage on an unselected bitline provides an optimal reference. (The second pulse also helps prepare the cell for restoration of its data state.) In some embodiments sensing occurs without a dummy cell, using an unselected bitline as a reference.
Advantages of the disclosed methods and structures include: A smaller cell area is realized in comparison with 2T2C cells; the disclosed scheme eliminates the complications of dummy cell schemes; a large voltage margin is available for accurate sensing; and good tolerance to power supply variations is achieved.